SystemVerilog-Style Constraints and Functional Coverage in Python

Matthew Ballance

https://www.fossi-foundation.org/latchup/#presentations

While SystemVerilog is the most widely-used language for creating functional verification testbench environments, many different language are used as well. In the past decade or so, Python has risen in popularity as a verification language. The open-source Python ecosystem for functional verification provides many of the expected elements of any other functional verification flow, such as libraries for connecting Python to simulators, frameworks for structuring testbench environments, and bus functional models for specific protocols. However, until recently, the it did not provide support for specifying data-randomization constraints and functional coverage metrics in a way that SystemVerilog users would find familiar. This presentation will introduce PyVSC, an open-source Python library for modeling SystemVerilog-style data randomization constraints and functional coverage metrics in Python. It will describe the constraint and coverage features that can be modeled with PyVSC, and describe how PyVSC leverages existing SMT solvers to generate random data from complex sets of constraints. It will describe how functional coverage data collected by PyVSC can be exported to support manipulation by external flows and toolchains.

OpenHardware

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OpenHardware

Sun Apr 2 09:30:00 2023 at UCSB Henley Hall room 1010