Make a basic CPU using a cheap FPGA《CPU自制入门》

Sharing on the RTL design, hardware design, and software design of a basic CPU. The 32-bit RISC ISA is from the reference book《CPU自制入门》. This book is one of the best beginner books on CPU design, the end product of the book is the AZ Processor SoC which you can run on an actual hardware.

I ported the AZ Processor SoC to run on the cheapest Altera FPGA (EP2C5T144C8N FPGA development board). My GitHub repo (RTL, output files, assembler, assembly programs, slides etc.):
https://github.com/endeneer/azpr-soc

Timestamps
00:00:00 Demo 1: Hello world UART printing
00:00:13 About the book《CPU自制入门》
00:01:04 System overview
00:02:50 Design of the 5-stage pipelined CPU
00:05:58 Structural hazard
00:07:18 Data hazard
00:17:51 Pipeline stall
00:19:56 Control hazard and branch delay slot
00:22:07 Interrupt and exception
00:26:10 Pipeline flush
00:31:44 Memory: RAM and ROM
00:36:33 Clock and reset
00:39:09 IO: GPIO, timer, and UART
00:41:52 Bus
00:46:00 ModelSim simulation, .do script and .wlf
00:53:43 FPGA pins assignment and circuit connection
00:56:16 Input board hardware design
00:57:48 Output board hardware design
00:58:26 FT232RL UART module connection
00:59:10 FPGA debugging with SignalTap Logic Analyzer
01:05:04 Software program loader design
01:06:20 XMODEM protocol
01:09:20 Demo 2: Transferring binary via XMODEM protocol
01:10:36 Demo 3: Kitchen timer with alarm

More projects coming soon~
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