Intel Quartus Prime Tutorial Part 4 Schematic | VHDL

Tutorial 01: Quartus Prime Tutorial

Introduction:
This tutorial provides an introduction to simulation of logic circuits using the Quartus Prime Simulator. The simulator used can perform functional simulation of a circuit specified in schematic block diagram, VHDL hardware description language and mixed VHDL and block schematic.
Procedure: Dr. UAK is guaranteed life insurance of your success!
a) Pre-laboratory
The required software is needed Quartus Prime Lite Edition (https://fpgasoftware.intel.com/16.0/?edition=lite) is needed to be pre-installed for this Tutorial.
b) The tutorial consists of 3-part tutorial. The basic steps involved in any VHDL design are
• Design a New Project
• Create schematic Block Diagram or write VHDL
• Simulate
• Debug if error occur. Making Changes and Re-simulating
• Generate Input and Output Wave using Run Functional Simulation
• Concluding Remarks


Design 1: Block Level Design
• Design a New Project
All 3 parts tutorials start with the setting up a new project from wizard. The following important settings are set during this process.
o Project Directory: As per our choice
o Project Name: example_schematic
o Device family: Cyclone V (E/GX/GT/SX/SE/ST)
o Avaitutorialle device: 5CSEMA5F31C6
• Create Schematic
A Block Diagram/Schematic File file is created and following logic circuit is drawn as shown below.



Figure 1 designstyle1: Block design file (*.bdf) of the schematic (example_schematic.bdf)
• Simulate
The schematic is simulated without any error.
• Generate Input and Output Wave using Run Functional Simulation

Figure 2 designstyle1: Simulation vector waveform file (.vwf) after the functional simulation of the schematic (example_schematic.vwf)


• Results
The output of the circuit was verified manually using the Boolean logic so circuit behave according to its schematic.


Design 2: VHDL Design
• Design a New Project
The following important settings are set during this process.
o Project Directory: As per our choice
o Project Name: example_vhdl
o Device family: Cyclone V (E/GX/GT/SX/SE/ST)
o Avaitutorialle device: 5CSEMA5F31C6
• Create VHDL file
A VHDL code is written to describe the logic circuit diagram.



Figure 3 designstyle2: VHDL source file (*.vhd) (example_vhdl.vhd)
• Simulate
The schematic is simulated without any error.
• Generate Input and Output Wave using Run Functional Simulation

Figure 4 designstyle2: Simulation vector waveform file (.vwf) after the functional simulation of the VHDL source code (example_vhdl.vwf)


• Results
The output of the VHDL was verified manually using the Boolean logic so circuit behave according to its schematic.
Design 3: Mixed Design (Both Block and VHDL)
• Design a New Project
The following important settings are set during this process.
o Project Directory: As per our choice
o Project Name: example_mixed1
o Device family: Cyclone V (E/GX/GT/SX/SE/ST)
o Avaitutorialle device: 5CSEMA5F31C6
• Create Schematic and VHDL
A VHDL code is written to describe the logic circuit diagram. And a block symbol is generated from Design1 example_schematic.



Figure 5 Tutorial1\designstyle3: VHDL source file (.vhd) (vhdlfunctions.vhd)
The block symbol of the example_schematic and vhdlfunctions is generated.

Figure 6 designstyle3: Block symbol file, vhdlfunctions.bsf, generated by Quartus for the sub-circuit represented by vhdlfunctions.vhd
Finally, the upper-level block diagram is made

Figure 7 designstyle3: Block design file (*.bdf) of the schematic (example_mixed1.bdf)
• Simulate
The schematic is simulated without any error.
Two important setting were set before simulation.
a) The example_schematic folder was defined in library so its symbol instance can be accessed from this design project.
b) The Top-Level entry was set to the block digram of mixed signal.
• Generate Input and Output Wave using Run Functional Simulation

Figure 8 designstyle3: Simulation vector waveform file (.vwf) after the functional simulation of the mixed schematic (example_mixed1.vwf)
• Results
The output of the VHDL was verified manually using the Boolean logic so circuit behave accordingly.
Conclusion:
The purpose of this tutorial is to provide a quick introduction to Quartus Prime, explaining only the rudimentary aspects of functional simulation that can be performed using the Quartus Prime Graphical User Interface. The 3 design projects were made and executed and their resultant graphs are shown above.


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