ECE 695 GPGPU-Sim Tutorial Part 1

Table of Contents:

00:13 - Marker
00:28 - Acknowledgements
00:29 - What GPGPU-Sim Models
01:22 - Dependencies
02:28 - Software Dependencies
03:28 - Software Dependencies – 2
03:39 - Installing CUDA on qstruct
04:22 - Building GPGPU-Sim
04:45 - Installing CUDA on qstruct
04:52 - Building GPGPU-Sim
08:08 - Marker
09:30 - Marker
11:00 - GPGPU-Sim Tutorial
11:02 - Acknowledgements
11:07 - Thread Hierarchy Revisited
11:08 - Running Apps
11:08 - Thread Hierarchy Revisited
11:28 - Warp = SIMT Execution of Scalar Threads
11:36 - GPU Microarchitecture Overview
11:37 - Warp = SIMT Execution of Scalar Threads
11:42 - GPU Microarchitecture Overview
11:55 - Inside a SIMT Core
12:02 - Inside a SIMT Core (3.0)
12:16 - Fetch + Decode
12:44 - Fetch + Decode
12:45 - Instruction Issue
16:39 - Scoreboard
17:12 - SIMT Stack
17:13 - Scoreboard
17:14 - SIMT Stack
17:27 - Operand Collector
17:27 - SIMT Stack
17:31 - Operand Collector
17:43 - ALU Pipelines
19:00 - Writeback
19:46 - Memory Unit
19:47 - Writeback
19:49 - Memory Unit
21:43 -
22:17 -
23:37 - Shared Memory
24:11 - Shared Memory (cont.)
24:43 - Shared Memory Bank Conflicts
25:18 - Global Memory
25:48 - Coalescing
25:49 - Global Memory
27:15 - Coalescing
28:53 - Coalescing (cont.)
28:54 - Coalescing
29:12 - Coalescing (cont.)
29:42 - L1 Data Cache
30:51 - L1 Data Cache
32:47 - Memory Access Tracking
33:50 - Miss Status Holding Registers
35:17 - Atomic Operations
36:55 - SIMT Core Model Multiple warp schedulers
37:50 - SIMT Core Cluster
39:16 - GPU Microarchitecture Overview
39:23 - Clock domains
39:58 - Clock Domain Crossing
39:59 - Interconnection Network Model
39:59 - Clock Domain Crossing
40:40 - Interconnection Network Model
41:41 -
42:32 - Interconnect Injection Interfaces
42:33 -
42:38 - Interconnect Injection Interfaces
42:39 - Interconnect Injection Interfaces
42:39 - Interconnect Injection Interfaces
42:40 -
42:41 - Interconnect Injection Interfaces
42:42 - Interconnect Injection Interfaces
42:42 - Interconnect Injection Interfaces
42:44 - Interconnect Injection Interfaces
42:45 - Interconnect Injection Interfaces
44:05 - Interconnect Injection Interfaces
44:06 - Interconnect Injection Interfaces
44:06 - Interconnect Injection Interfaces
44:07 - Interconnect Injection Interfaces
44:07 - Interconnect Injection Interfaces
44:08 - Interconnect Injection Interfaces
44:09 - Interconnect Injection Interfaces
44:24 - Interconnect Injection Interfaces
44:26 - GPU Microarchitecture Overview
44:27 - Interconnect Injection Interfaces
44:31 - GPU Microarchitecture Overview
45:22 - Memory Address Mapping
45:36 - GPU Microarchitecture Overview
45:42 - Memory Address Mapping
46:14 - Mem. Address Mapping (Cont.)
46:58 - Memory Partition
50:03 - L2 Cache Bank
50:03 - Memory Partition
50:30 - L2 Cache Bank
51:29 - DRAM
52:27 -
52:50 -
52:51 -
52:56 -
53:21 -
53:39 -
56:05 -