Pentium Pro (P6) Microprocessor Architecture

This is an IA -32 Architecture, which means that the internal registers are 32- bit long.
It has 12 stage super pipelined implementation , whose efficiency is 33% higher than that of Pentium.
This directly gives the ability to operate at higher clock frequencies compared to its predecessor.
P6 processor frequently designated as a CISC processor with RISC like features.
P6 is considered to have superscalar order of 3 , which means that on an average , it can handle three instructions at a time, i.e three instructions can be fetched , decoded , executed and retired per clock cycle.
Fetch /decode unit : this is an in-order unit takes instructions from the I –Cache ,and decodes them into a series of micro-ops

Dispatch/execute unit : this is an out of order scheduler for the micro-ops that takes into account all the data and structural hazards and allows execution after resolving them.

Retire unit: this is also in-order unit.it has knowledge of when instructions are completed so that they can be ‘committed’ or ‘retired’ This unit must not only take note of which micro-ops are complete , but must also arrange the results in the original program sequence.

The key feature of the Pentium p6 micro architecture is an innovative out-of-order execution technique that has been designated as ‘dynamic execution’.
Dynamic execution includes three data processing concepts:
Branch prediction
Dynamic scheduling
Speculative execution

Branch Prediction: is aimed at delivering high performance in super scalar microarchitectures.P6 implements a highly optimized Yeh and Patt (1991) branch prediction algorithm to predict the direction of the instruction stream through multiple levels of branches , procedure calls and returns.
Dynamic scheduling: is the scheme in which the flow of data is analysed at run time to determine data and register dependencies and to pave the way for out-of-order instruction execution.
Speculative execution : is the result of the above mentioned two techniques.

There are five functional units in the execution unit
The register alias table is part of the register rename logic
The decoding logic has three sections for catering to different levels of complexity of the instructions involved.
After decoding into micro codes , a sequencer sends them in to execution unit.
The retirement register file is the same as the ARF of the processor , because when an instruction is ‘retired’ , the results are stored in the registers of the processor.
The rename register file is included in the order buffer.
The memory order buffer is for reordering data in memory ; it is the part of the memory subsystem and interfaces the processors out-of-order engine with the memory.